1. Field of the Invention
This invention relates to a semiconductor integrated circuit of standard cell system having a cell layout whose design can be changed.
2. Description of the Related Art
The layout of cells in a standard cell system is made by use of a design support tool (CAD tool) by a computer.
As shown in FIG. 1, cells 92 necessary for constituting a circuit in a chip 91 are arranged in cell array regions 93 by use of the CAD tool and the cells are connected to each other via wirings 95 by use of wiring regions 94. I/O cells (input/output cells) 96 are arranged in an I/O cell array region 97 and respectively connected to desired cells via the wirings 95.
In the above cell layout, no-cell regions 98 and 99 in which no cells are arranged may occur. The main reason why such no-cell regions 98 and 99 occur is explained in detail below.
First, the area of the wiring region 94 is generally larger than that of the cell array region 93. Therefore, the cell arrangement is made such that the area of the wiring region 94 can be made as small as possible. As a result, in most cases, the sizes of the cell arrays of the cells 92 may become different from each other. Since the chip 91 is formed in a rectangular form, the region in which cells are arranged is defined by a rectangular region determined by the longest cell array, and as a result, no-cell regions 98 may be made on the right and left sides of each cell array.
Secondly, the no-cell regions 99 may sometimes be made not on the right and left sides of each cell array, but inside the cell array. Such a case may occur when no-cell regions 99 previously prepared at the cell arranging stage are not eventually used as wiring tracks at the wiring stage because of the presence of vertically crossing wirings.
In either case, only power source lines 100 for applying potentials to the cells can be arranged in the no-cell regions 98 and 99 in the prior art.
In the development of LSI, it is frequently necessary to change the design after the layout design is completed. In the development of complicated systems, it is extremely difficult to prevent occurrence of bugs (erroneous operations of the system). The bugs may be detected by evaluating experimental chips or by performing extensive simulations. In either case, it is frequently necessary to change the design in order to prevent the occurrence of bugs after the layout of the semiconductor chip is completed.
Further, it is sometimes necessary to change the design when the product standard or part of the specification is changed. In addition, the timing of signals is frequently adjusted by inserting a delay circuit. In most cases, the above design changes can be attained by partial modification of the circuit or addition of a circuit. In this case, if the above design changes can be attained by partial modification of the circuit or addition of a circuit without changing a large portion of the chip layout which has been already designed, it is preferable to do so instead of making a new layout design from the beginning because time and labor used for creating the design are not wasted. For example, when the layout of the chip is changed, the parasitic capacitance and resistance of the wiring are generally changed, causing the propagation delay to be changed, and requiring execution of simulations for checking whether a desired operation is correctly effected or not. If the design change can be attained by partial modification of the layout, verification can be made only by executing the simulation only for the modified portion. Particularly, when the timing of a signal is adjusted by inserting a delay circuit, the wiring layout which has been already made must be kept unchanged.
Further, as the manufacturing mask for forming a semiconductor chip which is required to be corrected by the layout change is used in a later step of the chip manufacturing process, time delay in the product developing schedule and financial burden caused by the design change can be reduced. For example, if the design change can be attained by changing the wiring (metal wiring and contact hole layer), a chip which has been subjected to manufacturing steps immediately before the wiring step may be subjected to the remaining steps according to the design change so that an increase in the time and cost required for the development of the chip can be reduced.
However, in the conventional standard cell design method, the circuit change attained by the wiring change is limited to a method of fixing a node (for example, an input or output terminal of a gate) of the circuit at a power source potential (V.sub.DD, V.sub.SS) or setting the same in an electrically floating state.
Since only transistors required for constituting an original circuit are arranged, new cells are additionally arranged and wired when a circuit is added. Therefore, correction of the chip manufacturing masks must be effected substantially in all of the steps starting from a mask used in the initial step of the manufacturing process and a new chip manufacturing process must be effected from the beginning.
Thus, in the prior art, when the design change must be effected after the layout design is completed, the layout design must be effected again from the beginning and a new chip manufacturing process must be effected from the initial step again.